Core Processes of Printer Chip Reverse Engineering---Netlist

Core Processes of Printer Chip Reverse Engineering---Netlist

Toner chip reverse engineering is a technology that strips the chip materials layer by layer through chemical methods and analyzes the internal structure of the chip using a scanning electron microscope (SEM). 

Attackers can infer the chip's functions and design code by extracting the circuit layout and gate - level netlist. This method is usually used to crack the design logic of the chip.

It is essentially a technology that reverse - deduces the printer chip design logic through physical deconstruction + micro - analysis, with a dual nature of “technical research” and “security risks”. 

This series article will help you understand this technology more comprehensively from four dimensions: core processes, key objectives, application scenarios (legal vs illegal), and protection methods:

In circuit design, a netlist is used to describe the connection relationships among circuit components. Generally, it is a text file that follows a relatively simple markup syntax.

Netlist

For complex integrated circuit designs, the circuit functions need to be completed through multiple levels of description.

System - level

The function and external characteristics of the circuit are defined. Designers only need to divide the circuit into several abstract functional modules and clearly define the logical functions of each functional module.

Architectural - level

At this level, the circuit is described as several interconnected typical logical components and state machines that control its data transfer. Typical logical components include counters, registers, arithmetic units, etc., also known as the data path. The state machine is a special part of a design. It controls the operation of the data path. Under the action of the clock, the state machine continuously undergoes state transitions according to the current state and input signals, and at the same time generates output signals to control the operation of each logical module.

Register - Transfer - Level (RTL)

The most important description in ASIC design must be completed using a hardware description language. The so - called register - transfer - level description is based on the understanding that any digital circuit, regardless of its function, is implemented by registers and combinational logic circuits between registers. Registers are used to store data, and combinational circuits are used to transfer data. RTL code must ensure synthesizability and only some description statements in the hardware description language can be used. The circuit structure should be vaguely visible from the RTL code, but it should not be written too specifically. Code that is refined to logic gates and flip - flops is not good because the conversion from RTL description to cells is the task of the logic synthesis tool. Writing to the cell level manually not only reduces the readability of the code but also is not conducive to optimization.

Gate - level and Transistor - level Generated by EDA tools

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